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EM250
(Re)start and stop segments are initiated by setting the register bits SC_I2CSTART or SC_I2CSTOP in the
SC2_I2CCTRL1 register, followed by waiting until they have cleared. Alternatively, the register bit
SC_I2CCMDFIN in the SC2_I2CSTAT can be used for waiting.
For initiating a transmit segment, the data has to be written to the SC2_DATA data register, followed by
setting the register bit SC_I2CSEND in the SC2_I2CCTRL1 register, and completed by waiting until it clears.
Alternatively, the register bit SC_I2CTXFIN in the SC2_I2CSTAT can be used for waiting.
A receive segment is initiated by setting the register bit SC_I2CRECV in the SC2_I2CCTRL1 register, waiting
until it clears, and then reading from the SC2_DATA data register. Alternatively, the register bit SC_I2CRXFIN
in the SC2_I2CSTAT can be used for waiting. Now the register bit SC_I2CRXNAK in the SC2_I2CSTAT register
indicates if a NACK or ACK was received from an I 2 C slave device.
Interrupts are generated on the following events:
?
?
?
?
?
?
Bus command ( SC_I2CSTART/SC_I2CSTOP ) completed (0 to 1 transition of SC_I2CCMDFIN )
Character transmitted and slave device responded with NACK
Character transmitted (0 to 1 transition of SC_I2CTXFIN )
Character received (0 to 1 transition of SC_I2CRXFIN )
Received and lost character while receive FIFO was full (Receive overrun error)
Transmitted character while transmit FIFO was empty (Transmit underrun error)
To generate interrupts to the CPU, the interrupt masks in the INT_SC2CFG and INT_CFG register must be
enabled.
5.3.3
SC2_MODE [0x442A]
Registers
15
0-R
0
0
0-R
7
14
0-R
0
0
0-R
6
13
0-R
0
0
0-R
5
12
0-R
0
0
0-R
4
11
0-R
0
0
0-R
3
10
0-R
0
0
0-R
2
9
0-R
0
0-RW
1
SC2_MODE
8
0-R
0
0-RW
0
SC2_MODE
[1:0]
SC2 Mode: 0 = disabled; 1 = disabled; 2 = SPI mode; 3 = I2C mode.
Note: To change between modes, the previous mode must be disabled first.
SC2_DATA [0x441E]
15
0-R
0
14
0-R
0
13
0-R
0
12
0-R
0
11
0-R
0
10
0-R
0
9
0-R
0
8
0-R
0
SC2_DATA
0-RW
7
0-RW
6
0-RW
5
0-RW
4
0-RW
3
0-RW
2
0-RW
1
0-RW
0
SC2_DATA
120-0082-000V Rev 1.1
[7:0]
Transmit and receive data register. Writing to this register pushes a byte onto the transmit
FIFO. Reading from this register pulls a byte from the receive FIFO.
Page 68
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